This invention relates to digital parallel processors or processor arrays of the type having a two dimensional matrix of substantially identical interconnected cells adapted to receive signals from other cells in the matrix to sequentially perform transformational operations on a plurality of input signals to produce an output based upon such operations.
There are many different examples of processor arrays in the prior art as exemplified in the above-identified related application. One of the most fundamentally referred to examples of a processor array is Unger U.S. Pat. No. 3,106,698, which discloses a two dimensional matrix of identical processing elements or cells having a logic and storage capability. Each cell is connected to a plurality of neighboring cells and input data or signals may be introduced directly into each cell from an equivalent cell via an input array. Processing in each cell is accomplished under the control of a master control which issues general orders to all of the cells to permit simultaneous processing of the data in each cell and transfer information between cells through multiplexor links. A series of transformations are performed on the input data by the cells to arrive at an output matrix.
From Unger there proceeds a whole realm of parallel processor array structures, many having a principal function of recognition, analization, digitization or classification of patterns or images. However, these arrays are aimed at precise and accurate results, that is for given inputs there will be definitive outputs, i.e., an output for each input so that different outputs may represent a particular pattern or image event, e.g., an edge. On the other hand, the processor array of this invention has an adaptive behavior, i.e., is capable of operating in a nonlinear manner so that various kinds of inputs come to mean certain desired outputs although the inputs may not necessarily be the same.